module ysyx_22040213_ram_axi(
	  input rst,
	  input clk,
  //-----------ar-----------------------//
  input i_axi_slave_arvalid,

  input [63:0] i_axi_slave_araddr,
//  input [3:0]  i_axi_slave_arid,
//  input [7:0]  i_axi_slave_arlen,
//  input [2:0]  i_axi_slave_arsize,
//  input [1:0]  i_axi_slave_arburst,
  output reg o_axi_slave_arready,  
  //------------r-----------------------//
  input i_axi_slave_rready,
  
  output reg o_axi_slave_rvalid,
  output reg [63:0] o_axi_slave_rdata, 
//------------aw-------------------------//
  output reg o_axi_slave_awready,

  input i_axi_slave_awvalid,
  input [63:0] i_axi_slave_awaddr,
//  input [3:0]  i_axi_slave_awid,
//  input [7:0]  i_axi_slave_awlen,
//  input [2:0]  i_axi_slave_awsize,
//  input [1:0]  i_axi_slave_awburst,

  //-------------w-----------------------//
  output reg o_axi_slave_wready,

  input i_axi_slave_wvalid,
  input [63:0] i_axi_slave_wdata,
  input [7:0]  i_axi_slave_wstrb,
//  input  i_axi_slave_wlast,

  //-------------b-----------------------//
  input i_axi_slave_bready,

  output o_axi_slave_bvalid
//  input [1:0] i_axi_master_bresp,
//  output reg [3:0] o_axi_slave_bid

);
	reg [63:0] ram_rdata;
//	reg [3:0]  ram_wid;

	/* verilator lint_off UNUSED */
	wire need = i_axi_slave_awaddr == 64'h830699c8 && i_axi_slave_wvalid;
	import "DPI-C" function void mpmem_read(input longint raddr, output longint rdata);
	import "DPI-C" function void mpmem_write(input longint waddr, input longint wdata, input byte wmask);
	always @(*) begin
		if(i_axi_slave_arvalid)begin
//		  mpmem_read(64'h00000000800000000, ram_rdata);
		  mpmem_read(i_axi_slave_araddr, ram_rdata);
		end
		if(i_axi_slave_wvalid)begin
//		  ram_wid = i_axi_slave_awid;
	      	  case(i_axi_slave_wstrb)
			8'h01 : mpmem_write(i_axi_slave_awaddr, i_axi_slave_wdata, 8'h01);//sb
			8'h03 : mpmem_write(i_axi_slave_awaddr, i_axi_slave_wdata, 8'h03);//sh
			8'h0f : mpmem_write(i_axi_slave_awaddr, i_axi_slave_wdata, 8'h0f);//sw
			8'hff : mpmem_write(i_axi_slave_awaddr, i_axi_slave_wdata, 8'hff);//sd 
			default : mpmem_write(i_axi_slave_awaddr, i_axi_slave_wdata, 8'b00000000);
		  endcase
		end else begin
		end
	end

reg [1:0] write_status;
reg [1:0] read_status;
always @(posedge clk)begin
  if(rst)begin
    write_status <= 2'b00;	  
    o_axi_slave_awready <= 1'b0;
    o_axi_slave_wready <= 1'b0;  
    o_axi_slave_bvalid <= 1'b0;
  end else begin
    case(write_status)
      2'b00: begin
	//ready to aw handshake
        write_status <= 2'b01;
	o_axi_slave_awready <= 1'b1;
      end
      2'b01: begin
        if(i_axi_slave_awvalid && o_axi_slave_awready)begin
	  o_axi_slave_awready <= 1'b0;
	  write_status <= 2'b10;
	  o_axi_slave_wready <= 1'b1;
        end else begin 
	  write_status <= 2'b01;
      	  o_axi_slave_awready <= 1'b1;
	  o_axi_slave_wready <= 1'b0;
	end
      end
      2'b10: begin
	if(i_axi_slave_wvalid && o_axi_slave_wready)begin
	  write_status <= 2'b11;
	  o_axi_slave_wready <= 1'b0;
	  o_axi_slave_bvalid <= 1'b1;
//	  o_axi_slave_bid <= ram_wid;
  	end else begin
	  o_axi_slave_awready <= 1'b0;
	  write_status <= 2'b10;
	  o_axi_slave_wready <= 1'b1;
	  o_axi_slave_bvalid <= 1'b0;
	end
      end
      2'b11: begin
        if(i_axi_slave_bready && o_axi_slave_bvalid)begin	  
	  o_axi_slave_bvalid <= 1'b0;
	  write_status <= 2'b00;
  	end else begin
  	  write_status <= 2'b11;
	end
      end
    endcase

    case(read_status)
      2'b00: begin
        read_status <= 2'b01;
	o_axi_slave_arready <= 1'b1;
      end
      2'b01: begin
	if(o_axi_slave_arready && i_axi_slave_arvalid)begin
	  o_axi_slave_arready <= 1'b0;
	  read_status <= 2'b10;
	  o_axi_slave_rvalid <= 1'b1;
	  o_axi_slave_rdata <= ram_rdata;//R valid read data valid 
	end else begin
          o_axi_slave_arready <= 1'b1;
	  read_status <= 2'b01;
	  o_axi_slave_rvalid <= 1'b0;
	end
      end
      2'b10: begin
        if(o_axi_slave_rvalid && i_axi_slave_rready)begin
	  o_axi_slave_rvalid <= 1'b0;
	  read_status <= 2'b00;
        end else begin
          o_axi_slave_rdata <= 64'b0;;
	  o_axi_slave_rvalid <= 1'b1;
	  read_status <= 2'b10;
	end
      end
      default: begin
        read_status <= 2'b00;
      end
    endcase
  end
end
endmodule




































